pastermil@sh.itjust.works to Programmer Humor@lemmy.ml · 10 months agoSome Mnemonicssh.itjust.worksexternal-linkmessage-square20linkfedilinkarrow-up1354arrow-down16
arrow-up1348arrow-down1external-linkSome Mnemonicssh.itjust.workspastermil@sh.itjust.works to Programmer Humor@lemmy.ml · 10 months agomessage-square20linkfedilink
minus-square9point6@lemmy.worldlinkfedilinkarrow-up27·10 months agoI still don’t know why this architecture went for a Double XOR as the NOP, I guess they were just flexing that the reference chip design could do both in a single cycle
minus-squarepancake@lemmygrad.mllinkfedilinkarrow-up4·edit-25 months agoThis content will be automatically deleted
I still don’t know why this architecture went for a Double XOR as the NOP, I guess they were just flexing that the reference chip design could do both in a single cycle
This content will be automatically deleted